1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor element. In addition, the invention relates to a semiconductor device which is capable of wireless data communication (hereinafter referred to as an ID tag).
2. Description of the Related Art
In recent years, a semiconductor device having a semiconductor element has been applied to various fields such as an electronic apparatus including a high performance personal computer and a portable information terminal, an IC card, and an ID tag, and developed to have higher capacity in accordance with the achievement of a higher-speed operation of a CPU (Central Processing Unit) included in the electronic apparatus, increase in the amount of process data and the amount of store data in an IC card and the like.
The semiconductor device having a semiconductor element as shown in FIG. 4 generally comprises a storage means (a memory cell array) 11 having memory cells 13 each including a memory element which is arranged in a plurality of regions where a bit line Bx (1≦x≦m, m is a positive integer) and a word line Wy (1≦y≦n, n is a positive integer; a row address selection line) cross each other with an insulator interposed therebetween, a selector circuit 14 including switches SWx (1≦x≦m, m is a positive integer) connecting to the bit lines respectively, a first decoder circuit 15 for selecting the switch in the selector circuit 14, and a second decoder circuit 16 for selecting the word line (see FIG. 4).
In a ROM (Read Only Memory, a memory dedicated to data reading) particularly, one transistor serves as the aforementioned memory element in many cases. Electrodes (a gate electrode, a source electrode, and a drain electrode) of the transistor are connected as follows: the gate electrode is connected to the word line, one of the source electrode and the drain electrode is connected to the bit line, and the other is connected to a high voltage power source line (VDD) 22 and a low voltage power source line (VSS) 23.
For example, in FIG. 5, as for a transistor as a memory element 18 in a memory cell, a gate electrode is connected to the word line W1, one of a source electrode and a drain electrode is connected to the bit line B1, and the other is connected to a high voltage power source line (VDD) 22. In such a case, the memory cell stores data of Hi level (1).
On the other hand, as for a transistor as a memory element 19 in a memory cell, a gate electrode is connected to the word line W1, one of a source electrode and a drain electrode is connected to the bit line B2, and the other is connected to a low voltage power source line (VSS) 23. In such a case, the memory cell stores data of Lo level (0).
Data may be stored in the following manners as well: data of Hi level (1) is stored when a high voltage power source line (VDD) being connected whereas data of Lo level (0) is stored when no transistor is provided, data of Hi level (1) is stored when a high voltage power source line (VDD) being connected whereas data of Lo level (0) is stored when a power source line being not connected, data of Lo level (0) is stored when a low voltage power source line (VSS) being connected whereas data of Hi level (1) is stored when no transistor is provided, and data of Lo level (0) is stored when a low voltage power source line (VSS) being connected whereas data of Hi level (1) is stored when a power source line being not connected.
The case of data reading in a ROM is briefly described below (see FIG. 5). One of the switches SW1 to SWm in the selector circuit 14 is selected by the first decoder circuit 15, and one of the bit lines Bx, which is connected to a source electrode or a drain electrode of a transistor as a memory element in a memory cell is selected. When the switch is selected, the selected bit line is connected to an output bus 12 (that is, current flows). In addition, one of the word lines, which is connected to a gate electrode of a transistor as a memory element in a memory cell, is selected by the second decoder circuit 16.
Selected in this manner is only a memory cell in a region where the bit line and the word line, which are selected by the first and second decoder circuits 15 and 16 and the selector circuit 14, cross each other through an insulator. That is, a bit line is connected to a drain electrode or a source electrode of a transistor as a memory element in the memory cell, and then data corresponding to the connection state is read out by the output bus 12 which is connected to the bit line. For example, when a memory cell including the transistor 19 as a memory element is selected by the first and second decoder circuits 15 and 16 and the selector circuit 14, a bit line B2 which is connected to one of the source electrode and the drain electrode of the transistor 19 is connected to the low voltage power source line (VSS) 23 which is connected to the other of the source electrode and the drain electrode, and then data of Lo level (0) of the low voltage power source line (VSS) 23 is read out by the output bus 12 which is connected to the bit line B2.
The case of data reading in the ROM is briefly described above. Each word line selected by the second decoder circuit 16 is connected to not only a gate electrode of a transistor in a memory cell to be read data but also to each gate electrode of a plurality of transistors. Therefore, the state between each source electrode and each drain electrode of the transistors is conductive at the same time. As described above, one of a drain electrode and a source electrode of a transistor is generally connected to a power source line such that data in the memory cell is shown. Thus, the conductive state between each source electrode and each drain electrode of the plurality of transistors at the same time results in an unnecessary current flowing to the power source line, leading to a large current consumption. As a semiconductor device including memory elements for storing data has been developed to have higher capacity, the memory cell array 11 having memory cells 13 each including the memory element occupies a larger area of a chip and the number of transistors connected to one word line selected for reading data is increased, that is, the amount of unnecessary current flowing to a power source line upon selecting the word line is increased and a current consumption is increased.
In addition, when a current consumption is increased, voltage drop of a power source may occur and accurate data reading may not be carried out.